This invention relates to a memory system, and more particularly to a random access memory system. More concretely, it relates to a semiconductor memory system which is formed on a large-scale integrated circuit comprised of MOSFET's. More specifically, it relates to a memory system with a memory sense circuit which detects stored signals of memory cells utilizing one-transistor cells at higher speed and at higher sensitivity.
In a semiconductor memory utilizing one-transistor cells, a signal read out from a memory cell is very small. In order to realize a high-speed random access memory, accordingly, it is important to detect the small signal at high speed. A technique for the high-speed detection is described in a co-pending U.S. patent application Ser. No. 644,855, entitled "A Memory System with a Sense Circuit," filed on Mar. 31, 1976 by the same applicant, and assigned to the same assignee as those of the present application.
The memory system described in the aforecited application utilizes a pair of first and second data lines to which a plurality of memory cells are connected. Each data line has first and second data line portions, and a first flip-flop type differential amplifier which connects both the portions.
The first and second data lines are respectively connected to first and second input lines through first and second switching elements, and the first and second input lines are further connected to a second differential amplifier. After precharging the first and second input lines and the first and second data lines to a precharge voltage of approximately a half of a supply voltage in advance, one of the memory cells is read out. In this case, either a voltage signal which is higher than the precharge or a voltage signal which is lower than the same is stored in the memory cell beforehand. As a result, the potential of the data line portion with the memory cell connected thereto becomes higher or lower than the precharge voltage, depending on the stored signal of the memory cell read out. At this time, the potential of the other data line portion which pairs with the above-cited data line portion becomes lower or higher than the precharge voltage by the action of the first flip-flop type differential amplifier. After all, each data line portion becomes higher or lower than the precharge voltage according to the stored signal read out.
Accordingly, either the first or second switching element connected to this data line is rendered conductive, whereby the voltage of one of the two input lines can be shifted to a voltage higher or lower than the original precharge voltage in dependence on the signal read out from the memory cell. At this time, the other input line is held at the original precharge voltage. Therefore, using the original precharge voltage as a reference voltage, the difference of the voltages of the first and second input lines are amplified speedily by the second differential amplifier.
In the memory system constructed as described above, the stored signal of the memory cell can be detected at higher speed than in the past owing to the actions of the first and second flip-flop type differential amplifiers. In such a memory system, however, the operating speed of the first and second flip-flop type differential amplifiers is not satisfactorily high yet. In the foregoing memory system, by the differential amplifiers, the voltage of one of the pair of data lines and the voltage of one of the pair of input lines are raised so as to become higher than the original precharge voltage, and the voltage of the other is lowered so as to become lower than the original precharge voltage. The flip-flop type differential amplifier however requires a longer time for raising the output voltage than for lowering it. Accordingly, supposing now the first case where the first signal with a higher voltage is read out from a memory cell and the corresponding switching element is turned "on" when a certain time has lapsed after starting the amplification of the first signal by the first differential amplifier, and the second case where the second signal with a lower voltage is read out from the memory cell and the corresponding switching element is turned "on" when the same time has lapsed after starting the amplification of the second signal by the first differential amplifier, the difference between the voltage of the input line onto which the first signal is read out and the precharge voltage on the other input line is smaller than the difference between the voltage of the input line onto which the second signal is read out and the precharge voltage on the other input line. Consequently, the precharge voltage which is one of the two input signals to the second differential amplifier does not lie substantially middle between the two, high and low levels which the other input signal can assume, but it is closer to the high level. Therefore, when the other input signal is at the high level, the difference between this input signal and the precharge voltage is smaller than when it is at the low level, so that the corresponding switching element must be turned "on" when a longer time has lapsed after starting the amplification by the first differential amplifier. Otherwise, the difference between the input signal of the high level and the precharge voltage cannot be made sufficiently large, and the second differential amplifier provides an erroneous output. For the reason described above, it takes a long period of time before the amplified signal of a signal stored in a memory cell is provided as an output from the second differential amplifier.
Further, for the high-speed detection, the flip-flop type differential amplifier should desirably be one which decreases the voltage of one input signal without increasing the voltage of the other input signal. Such a flip-flop type differential amplifier has been already known. An example is constructed of a pair of cross-connected transistors, no load transistor being connected to the transistors, and it is called the dynamic flip-flop. In employing the dynamic flip-flops as the first and second differential amplifiers described before, it is desirable to make the precharge voltage of the data lines and the input lines a supply voltage or a voltage of close thereto. For securing the amplification by the first amplifier, either of two voltages lowered by different values from the precharge voltage in is stored into each memory cell. Accordingly, when the first data line is coupled with the first input line after reading out the memory cell connected to the first data line, the voltage of the first input line becomes lower than the original precharge voltage at all times irrespective of the stored signal of the memory cell. Consequently, the other or second input line onto which the stored signal of the memory cell is not read out and which is held at the precharge voltage is always higher in voltage than the first input line onto which the stored signal of the memory cell has been read out. For this reason, the second differential amplifier does not provides a signal corresponding to the stored signal of the memory cell. Accordingly, the dynamic flip-flop cannot be used as the second differential amplifier, with the result that the high-speed operation cannot be achieved.